Production method for a semiconductor component

ABSTRACT

A method for fabricating a semiconductor component includes: deposition of a polysilicon layer on a substrate, deposition of a precursor layer on the polysilicon layer, and deposition of a protective layer on the precursor layer. A crystalline transformation occurs in the precursor layer at a first temperature to form an electrode layer. The layers are patterned to form an electrode stack, and the polysilicon layer is oxidized at a second temperature such that no crystalline transformation occurs in the electrode layer.

The present invention relates to a method for fabricating asemiconductor component having a substrate and an electrode stack whichis arranged on the substrate and includes a polysilicon electrode layerand a tungsten-containing electrode layer above it.

The term substrate is to be understood in the general sense and maytherefore comprise both single-layer and multilayer substrates of anydesired type.

Although it can be applied to any desired semiconductor components, thepresent invention as well as the problem on which it is based areexplained with reference to gate electrode stacks of dynamic randomaccess memories (DRAMs) using silicon technology.

BACKGROUND

What are known as single-transistor cells are used in dynamic randomaccess memories (DRAMs). These cells comprise a storage capacitor and aselect transistor (MOSFET), which connects the storage electrode to thebit line. The storage capacitor may be designed as a trench capacitor oras a stacked capacitor.

To drive the select transistor, a metalically conductive gate electrodestack is placed onto the gate oxide. Typical gate electrode stacks arestacks comprising doped polysilicon and, above it, a tungsten silicide(WSi_(x)) or a tungsten nitride/tungsten sandwich.

Patterning of a gate electrode stack of this type, for example by aplasma etch, by means of an additional silicon nitride capping layer onthe upper tungsten-containing electrode layer, together withcorresponding gate contacts, provides the metallic connection lines.

The patterned gate electrode stacks are usually subjected to a thermalaftertreatment in such a manner that simultaneously the uncovered sidewalls are partially oxidized and the resistance in the metal isminimized by targeted phase transformation or grain growth. The thinfilm of oxide which is thereby formed on the side walls of thepolysilicon improves the leakage current characteristics of thetransistors and acts as a spacer for the subsequent LDD (lightly dopeddrain) implantation. The latter sets the transistor parameters over thedefined gate length. The metallic phase transformation at typicaltemperatures of 1000 to 1080° C. leads to a reduction in the resistanceand is associated with strong grain growth in the gate metal.

In the process as currently used, the conditioning takes place atbetween 1000 and 1080° C. after the patterning of the gate electrodestack immediately before the LDD implantation. This known process leadsto the following problems.

When tungsten silicide (WSi_(x)) is used, grains grow out laterallybeyond the side faces of the gate electrode stack, which have beenetched smooth, forming a partial alloy with the polysilicon below. Theselateral projections, in particular in future technology generations witha feature size of <170 nm, may lead to short circuits with adjacentmetal contacts, since they may be etched open during the contact etch.

DRAM technologies with transistor gate lengths of less than 110 nmrequire modified cell architectures with lower resistances andconnections which are free of short circuits.

The use of tungsten without Si alloy with a tungsten nitride diffusionbarrier with respect to the polysilicon below fulfils the requirementsrelating to the resistance. However, tungsten as gate metal is notsuitable for current processes, since during the subsequent processinginvolved in thermal and oxidation processes, it escapes as a gas orsublimes as WO_(x) and is precipitated at the chamber inner walls,making it impossible to control the side wall oxidation.

SUMMARY

The object of the present invention is to provide an improved method forfabricating a semiconductor component of the type described in theintroduction which is able to prevent WSi_(x) grains from growing outand to prevent WO_(x) from being sublimed.

The general idea on which the present invention is based consists inseparating the thermal aftertreatment of the gate electrode stack (phasetransformation or grain growth in order to reduce the resistance) fromthe aftertreatment of the polysilicon (side wall oxidation), in twoindependent process steps.

All the known deposition and etching processes can be retained in thesame form. All the subsequent thermal processes can take place at lowertemperatures than has hitherto been the case, since the conditioning ofthe gate metal has been concluded, and this has a beneficial effect onthe heat budget.

Particular advantages of conditioning with a combination of tungstennitride/tungsten result from a lower stack height being required toachieve the same resistance. This results in a less demanding aspectratio during application of the insulation layer and simplifiessubsequent etching processes.

According to a preferred refinement, grain growth and/or phasetransformation associated with a reduction in the resistance takes placein the precursor layer at the first temperature.

According to a further preferred refinement, the tungsten-containingprecursor layer consists of tungsten silicide, the first temperaturelying in the range from 900 to 1080° C.

According to a further preferred refinement, the tungsten-containingprecursor layer consists of tungsten metal, with the first temperaturelying in the range from 900 to 1080° C.

According to a further preferred refinement, a diffusion barrier layermade from tungsten nitride is provided beneath the tungsten-containingprecursor layer made from tungsten metal during the deposition of thelayer sequence.

According to a further preferred refinement, the protective layer isformed into a hard mark by means of a lithographic process, and thelayer sequence is patterned by means of an etching process using thishard mask.

According to a further preferred refinement, the second temperature liesin the range from 800 to 850° C.

According to a further preferred refinement, the electrode stack is agate electrode stack which is located on a gate oxide layer of thesubstrate.

BRIEF DESCRIPTION OF THE DRAWINGS

An exemplary embodiment of the invention is illustrated in the drawingsand is explained in more detail in the description which follows.

FIGS. 1 a-e show the steps of an exemplary embodiment of the fabricationmethod according to the invention which are essential to gaining anunderstanding of the invention; and

FIG. 2 shows a further exemplary embodiment of the fabrication methodaccording to the invention.

DETAILED DESCRIPTION

In accordance with FIG. 1 a, first of all a substrate 1 is provided,this substrate having active regions (not shown), such as for examplesource regions and drain regions. First of all, a gate oxide layer 5 isformed on the substrate 1 by means of a standard thermal oxidationprocess. A doped polysilicon layer 7 is deposited on the gate oxidelayer 5, for example by means of the CVD (chemical vapor deposition)process. A tungsten silicide layer 9 is deposited on the polysiliconlayer 7 by means of a CVD process.

In a further exemplary embodiment as shown in FIG. 2, a tungsten nitridelayer 9 a is deposited, followed by the deposition of a tungsten layer 9b in the same process chamber.

Finally, a silicon nitride layer 11 is deposited, likewise by means of aCVD process. From here on, the process steps are once again identicalfor both exemplary embodiments.

In the following process step, which is illustrated in FIG. 1 b, a firstconditioning step takes place at a first temperature T1 in the rangefrom 900 to 1080° C., preferably 1000° C. This first conditioning stepbrings about phase transformation associated with a grain growth and areduction in the resistance of the tungsten silicide layer 9,transforming this precursor layer into the final electrode layer 9′.

In other words, the first conditioning step (900 to 1080° C.) is carriedout for phase transformation, grain growth or resistance reduction afterall the layers polysilicon, gate metal, silicon nitride have beencompletely deposited, i.e. with a capping layer above the gate metal,and prior to patterning of the gate electrode stacks. The sublimation oftungsten oxide (WO_(x)) can be prevented by the capping layer.Furthermore, the formation of surface roughness (cavities caused bygrain growth), which is inevitable during the phase transformation, andthe nitride layer above is prevented. Therefore, in particular there isno silicon nitride in the cavities, which during a subsequent gate stacketch would have a masking action in the cavities and would thereforelead to short circuits.

In the next method step, the silicon nitride layer 11 is patterned toform a hard mask 11′ by means of a standard photolithography step,leading to the state shown in FIG. 1 c.

This hard mark 11′ is then used to form the gate electrode stack fromthe layer sequence comprising the layers 5, 7, 9′ by means of a standardplasma-RIE step. This is illustrated in FIG. 1 d. Then, the remainingpolysilicon layer 7 is oxidized, in order to form side wall oxidespacers 13, in an oxidation furnace or by means of a rapid thermaloxidation process. This leads to the state shown in FIG. 1 e.

The second temperature step takes places at significantly lowertemperatures of 800 to 850° C. after the gate stack has been patterned,for the purpose of targeted side wall oxidation of the polysiliconsurfaces. Therefore, in the case of tungsten silicide (WSi_(x)), thelateral growth of the metal grains does not occur and the geometry ofthe pattern is retained, since after the gate stack etch the process ofgrain size growth or phase transformation in the gate metal hasconcluded.

The subsequent process steps are well known from the prior art andrequire no further explanation at this point. In particular, theabovementioned LDD implantation is carried out in a subsequent processstep.

Although the present invention has been described above on the basis ofa preferred exemplary embodiment, it is not restricted to thisembodiment, but rather can be modified in numerous ways.

In particular, the invention can be applied to any desired componentsand is not limited to gate electrode stacks.

1. A method for fabricating a semiconductor component, the methodcomprising: providing a substrate, depositing a polysilicon layer on thesubstrate, depositing a precursor layer on the polysilicon layer,depositing a protective layer on the precursor layer, after depositingthe protective layer, causing a crystalline transformation in theprecursor layer at a first temperature, the crystalline transformationforming an electrode layer, patterning the polysilicon layer, electrodelayer, and protective layer to form an electrode stack, and oxidizingthe polysilicon layer at a second temperature such that no crystallinetransformation occurs in the electrode layer, the second temperaturebeing less than the first temperature.
 2. The method of claim 1 furthercomprising selecting the precursor layer to include tungsten.
 3. Themethod of claim 1, wherein oxidizing the polysilicon comprises forming asidewall spacer.
 4. The method of claim 1, wherein causing a crystallinetransformation includes reducing the resistance in the precursor layer.5. The method of claim 1, further comprising selecting the precursorlayer to include a tungsten silicide material.
 6. The method of claim 1,further comprising selecting the first temperature to be between 900° C.and 1080° C.
 7. The method of claim 1, further comprising providing adiffusion barrier layer beneath the precursor layer.
 8. The method ofclaim 7, further comprising selecting the diffusion barrier layer toinclude tungsten nitride.
 9. The method of claim 1, further comprisingforming a hard mask from the protective layer.
 10. The method of claim9, wherein patterning the layers further comprises etching areas exposedby the hard mask.
 11. The method of claim 1, further comprisingselecting the second temperature to be between 800° C and 850° C. 12.The method of claim 1, further comprising providing a gate oxide layerbetween the substrate and the polysilicon layer.